Various embodiments disclosed herein relate generally to semiconductor technology and, more particularly, to a circuit for small swing data line and a method of operating the same.
In semiconductor integrated circuits, it is not uncommon for some internal interconnect lines to be highly capacitive. Such interconnect lines can be highly capacitive because they interconnect a large number of circuit elements, such as transistors, together, and also may extend long distances and over other elements that can further increase the capacitance on these lines. Often times, such highly capacitive interconnect lines are in the critical data path and need to be switched at high speeds. Switching such high capacitive lines at high frequencies can cause significant increases in dynamic power consumption and cause degradation of internal supply voltages (e.g., by causing ground bounce). Additionally, switching such highly capacitive lines between the supply rails at high speeds requires proper buffering and sizing of driver circuits which in turn can lead to even greater power consumption and further degradation of internal supply voltages.
One such integrated circuits that internally transmits data on highly capacitive interconnect lines is a DRAM (Dynamic Random Access Memory). A DRAM is a type of volatile memory that includes memory cells, each of which is composed of a transistor and a capacitor to store data. Data input/output operations as basic functions of a DRAM cell are carried out by turning on/off a word line serving as a gate input to a transistor in the DRAM cell.
The memory cell region in a memory device is typically divided into a plurality of banks. Data stored in each cell is read by transferring the cell data amplified by an IO (Input/Output) sense amplifier to a DQ block via a global IO line. Write data is written to a memory cell by transferring externally provided data input through a DQ block to a write driver via a global IO line and then storing the transferred data in the memory cell. Global IO lines, which are in the critical data path, interconnect many circuit elements and extend over long distances, and as such are highly capacitive.
As the demand continues to rise for highly integrated ICs (such as memory devices) that are capable of operating at higher speeds while consuming less power, achieving these two competing goals becomes increasing more difficult. Further, as operating speeds of highly integrated ICs increases, degradation of internal power supply lines becomes more pronounced. Thus, techniques that improve operating speeds, reduce power consumption, and improve upon the internal supply degradations are highly desirable.